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HT7044A データシート(PDF) 5 Page - SYC Electronica

部品番号 HT7044A
部品情報  TinyPowerTM Voltage Detector
PDF  16 Pages
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メーカー  SYC [SYC Electronica]
ホームページ  https://www.sycelectronica.com.ar/index.php
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HT7044A データシート(HTML) 5 Page - SYC Electronica

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HT7044A-1
Ta=25
°C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Conditions
VDET
Detection Voltage
¾¾
4.268
4.400
4.532
V
VHYS
Hysteresis Width
¾¾
0.02
VDET
0.05
VDET
0.1
VDET
V
IDD
Operating Current
8V
No load
¾
47
mA
VDD
Operating Voltage
¾¾
1.5
¾
24
V
IOL
Output Sink Current
3.6V
VOUT=0.36V
36
¾
mA
D
D
V
T
DET
a
Temperature Coefficient
¾
0
°C<Ta<70°C
¾±0.9
¾
mV/
°C
HT7050A-1
Ta=25
°C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Conditions
VDET
Detection Voltage
¾¾
4.850
5.000
5.150
V
VHYS
Hysteresis Width
¾¾
0.02
VDET
0.05
VDET
0.1
VDET
V
IDD
Operating Current
8V
No load
¾
47
mA
VDD
Operating Voltage
¾¾
2.1
¾
24
V
IOL
Output Sink Current
3.6V
VOUT=0.36V
36
¾
mA
D
D
V
T
DET
a
Temperature Coefficient
¾
0
°C<Ta<70°C
¾±0.9
¾
mV/
°C
HT70XXA-1
Rev. 1.40
5
January 26, 2006
Functional Description
The HT70XXA-1 series is a set of voltage detectors
equipped with a high stability voltage reference which is
connected to the negative input of a comparator
¾
denoted as VREF in the following figure for NMOS output
voltage detector.
When the voltage drop to the positive input of the
comparator (i,e,VB) is higher than VREF, VOUT goes
high, M1 turns off, and VB is expressed as VBH=VDD
´
(RB+RC)/(RA+RB+RC). If VDD is decreased so that VB
falls to a value less than VREF, the comparator output
inverts from high to low, VOUT goes low, VC is high, M1
turns on, RC is bypassed, and VB becomes: VBL=VDD
´
RB /(RA+RB), which is less than VBH. By so doing, the
comparator output will stay low to prevent the circuit
from oscillating when VB
» VREF.
If VDD falls below the minimum operating voltage, the
output becomes undefined. When VDD goes from low to
VDD
´ RB /(RA+RB)>VREF, the comparator output and
VOUT goes high.
The detectable voltage is defined as:
VDET (
-)=
R+ R + R
R+ R
AB
C
BC
´ VREF
The release voltage is defined as:
VDET (+) =
R+ R
R
AB
B
´ VREF
The hysteresis width is:
VHYS =VDET (+)
- VDET (-)
The figure demonstrates the NMOS output type with
positive output polarity (VOUT is normally open, active
low). The HT70XXA-1 series also supplies options for
other output types with active high outputs. Application
circuits shown are examples of positive output polarity
(normally open, active low) unless otherwise specified.
V S S
V D D
R A
R B
R C
M 1
M N
C o m p a r a t o r
V O U T
R L
V R E F
V B
V C
NMOS Output Voltage Detector (HT70XXA-1)



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