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ISD5216PI データシート(PDF) 30 Page - Winbond |
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ISD5216PI データシート(HTML) 30 Page - Winbond |
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30 / 75 page  ISD5216 - 30 - CFG2 Bit no. Signal Description D0 (LSB) ADPD Power down the Analog to Digital converter D1 DAPD Power down the Digital to Analog converter D2 LAW0 Select digital μ-Law or A-Law input/output format D3 LAW1 Select digital μ-Law or A-Law input/output format D4 I2S0 Select the I2S interface D5 HSR0 Enable the high sample rate mode D6 HPF0 Enable High Pass Filter D7 MUTE Mute the CODEC A/D and D/A path D8 CKDV Divide MCLK by 2560 or 1728 for 8 kHz ChipCorder sample rate D9 COG0 Output gain setting for the Digital to Analog converter D10 COG1 Output gain setting for the Digital to Analog converter D11 COG2 Output gain setting for the Digital to Analog converter D12 CKD2 Divide MCLK frequency by 2 or 1 D13 - Reserved D14 - Reserved D15 (MSB) - Reserved |
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