SS

SCK

SI

SO

Don't Care

A6

A5

A4

A3

A2

A1

A0

R/W

0

D7

D6

D5

D4

D3

D2

D1

D0

SS

SCK

SI

SO

A6

A5

A4

A3

A2

A1

A0

1

R/W

D7

D6

D5

D4

D3

D2

D1

D0

25

LP55281

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SNVS458D – JUNE 2007 – REVISED OCTOBER 2016

Product Folder Links: LP55281

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Copyright © 2007–2016, Texas Instruments Incorporated

7.5 Programming

The LP55281 supports two different interface modes:

•

SPI Interface (4-wire, serial)

•

I2C Compatible Serial Bus Interface

User can define the serial interface by IF_SEL pin. If IF_SEL = 0, I2C mode is selected.

7.5.1 SPI Interface

The LP55281 is compatible with SPI serial-bus specification and it operates as a slave. The transmission

consists of 16-bit write and read cycles. One cycle consists of a 7 address bits, 1 read/write (RW) bit and 8 data

bits. RW bit high state defines a write cycle and low a read cycle. SO output is normally in high-impedance state

and it is active only when data is sent out during a read cycle. A pullup resistor may be needed in SO line if a

floating logic signal can cause unintended current consumption in the input circuits where SO is connected. The

Address and Data are transmitted MSB first. The slave select signal (SS) must be low during the cycle

transmission. SS resets the interface when high and it has to be taken high between successive cycles. Data is

clocked in on the rising edge of the clock signal (SCK), while data is clocked out on the falling edge of SCK.

Figure 18. SPI Write Cycle

Figure 19. SPI Read Cycle

7.5.2 I2C Compatible Serial Bus Interface

7.5.2.1 Interface Bus Overview

The I2C compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the devices

connected to the bus. The two interface lines are the serial data line (SDA) and the serial clock line (SCL). These

lines should be connected to a positive supply, via a pullup resistor and remain HIGH even when the bus is idle.

For every device on the bus is assigned a unique address and it acts as a master or a slave, depending on

whether it generates or receives the SCL. When LP55281 is connected in parallel with other I2C compatible

devices, the LP55281 supply voltages VDD1, VDD2 and VDDIO must be active. Supplies are required to make sure

that the LP55281 does not disturb the SDA and SCL lines.