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LAN9252/ML データシート(PDF) 211 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 211 Page - Microchip Technology |
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211 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 211 LAN9252 To perform a read of the EtherCAT Process RAM, the read cycle is initiated by first writing the EtherCAT Process RAM Read Address and Length Register (ECAT_PRAM_RD_ADDR_LEN) with the starting byte address and length (in bytes) of the desired transfer followed by a write to the EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD) with the PRAM Read Busy (PRAM_READ_BUSY) bit set. Valid data, as indicated by the PRAM Read Data Available (PRAM_READ_AVAIL) bit in the EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD) is read from the FIFO through the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA). The PRAM Read Data Available Count (PRAM_READ_AVAIL_CNT) field indi- cates how many reads can be performed without needing to check the status again. Following the final read of the Eth- erCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA), the PRAM Read Busy (PRAM_READ_BUSY) self- clears. As the data is transferred from the EtherCAT Core into the FIFO the PRAM Read Length (PRAM_READ_LEN) and PRAM Read Address (PRAM_READ_ADDR) are updated to show the progress. Based on the starting address, the valid bytes in the first FIFO read are as follows: Based on the starting address and length, the valid bytes in the last FIFO read are as follows: Note: The starting byte address and length must be programmed with valid values such that all transfers are within the bounds of the Process RAM address range of 1000h to 1FFFh. Note: The final read of the EtherCAT Process RAM Read Data FIFO (ECAT_PRAM_RD_DATA) implies that all four bytes have been read, even if not all bytes are required. TABLE 12-7: ETHERCAT PROCESS RAM VALID FIRST READ BYTES Starting Address[1:0] 00b bytes 3, 2, 1 and 0 01b bytes 3, 2 and 1 10b bytes 3 and 2 11b byte 3 TABLE 12-8: ETHERCAT PROCESS RAM VALID LAST READ BYTES Starting Length[1:0] Starting Address[1:0] 01b (e.g. 5, 9, etc.) 10b (e.g. 6, 10, etc.) 11b (e.g. 7, 11, etc.) 00b (e.g. 8, 12, etc.) 00b byte 0 bytes 1 and 0 bytes 2, 1 and 0 bytes 3, 2, 1 and 0 01b bytes 1 and 0 bytes 2, 1 and 0 bytes 3, 2, 1 and 0 byte 0 10b bytes 2, 1 and 0 bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 11b bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 bytes 2, 1 and 0 |
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