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LAN9252/ML データシート(PDF) 215 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 215 Page - Microchip Technology |
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215 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 215 LAN9252 12.13.1 ETHERCAT PROCESS RAM READ DATA FIFO (ECAT_PRAM_RD_DATA) This read only register is used in conjunction with the EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD) and the EtherCAT Process RAM Read Address and Length Register (ECAT_PRAM_RD_ADDR_LEN) to perform read operations of the EtherCAT Core Process RAM. Data read from this register is only valid if the PRAM Read Data Available (PRAM_READ_AVAIL) bit in the EtherCAT Process RAM Read Command Register (ECAT_PRAM_RD_CMD) is a 1. The host should not read this register unless there is valid data available. Offset: 000h-01Ch Size: 32 bits Bits Description Type Default 31:0 EtherCAT Process RAM Read Data (PRAM_RD_DATA) This field contains the value read from the EtherCAT Core Process RAM. Note: Some bytes maybe invalid based on the starting address and transfer length. RO - |
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