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LAN9252/ML データシート(PDF) 272 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 272 Page - Microchip Technology |
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272 / 329 page  LAN9252 DS00001909A-page 272 2015 Microchip Technology Inc. 12.14.60 SYNCMANAGER[3:0] REGISTERS The device includes 4 SyncManagers. Each SyncManager is described in 8 Bytes, starting at 0800h. Table 12-17 details the base address for each SyncManager. The subsequent SyncManager registers will be referenced as an offset from these various base addresses. The variable “x” is used in the following descriptions to represent SyncManagers 0 through 3. 12.14.60.1 SyncManager x Physical Start Address Register Note 35: This register can only be written if the corresponding SyncManager is disabled via the SyncManager Enable/Disable bit of the SyncManager x Activate Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.60.2 SyncManager x Length Register Note 36: This register can only be written if SyncManager x is disabled via the SyncManager Enable/Disable bit of the SyncManager x Activate Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. TABLE 12-17: SYNCMANAGER X BASE ADDRESSES SyncManager Base Address 0 0800h 1 0808h 2 0810h 3 0818h Offset: SyncManager x Base Address +0h-1h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 Physical Start Address Specifies the first byte that will be handled by SyncManager x. R/W Note 35 RO 0000h Offset: SyncManager x Base Address +2h-3h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 Length Number of bytes assigned to SyncManager x. (This field shall be greater than 1, otherwise the SyncManager is not activated. If set to 1, only Watchdog Trigger is generated, if configured.) R/W Note 36 RO 0000h |
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