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LAN9252/ML データシート(PDF) 271 Page - Microchip Technology

部品番号 LAN9252/ML
部品情報  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252/ML データシート(HTML) 271 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 271
LAN9252
12.14.59.8 FMMUx Activate Register
12.14.59.9 FMMUx Reserved Register
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
Offset:
FMMUx Base Address +Ch
Size:
8 bits
Bits
Description
ECAT
Type
PDI
Type
Default
7:1
RESERVED
Write as 0.
RO
RO
0000000b
0
FMMU Activation
0:
FMMUx Deactivated
1:
FMMUx Activated. FMMUx checks logical addressed blocks
to be mapped according to the configured mapping.
R/W
RO
0b
Offset:
FMMUx Base Address +Dh-Fh
Size:
24 bits
Bits
Description
ECAT
Type
PDI
Type
Default
23:0
RESERVED
Write as 0.
RO
RO
000000h



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