データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

LAN9252/ML データシート(PDF) 268 Page - Microchip Technology

部品番号 LAN9252/ML
部品情報  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252/ML データシート(HTML) 268 Page - Microchip Technology

Back Button LAN9252/ML Datasheet HTML 264Page - Microchip Technology LAN9252/ML Datasheet HTML 265Page - Microchip Technology LAN9252/ML Datasheet HTML 266Page - Microchip Technology LAN9252/ML Datasheet HTML 267Page - Microchip Technology LAN9252/ML Datasheet HTML 268Page - Microchip Technology LAN9252/ML Datasheet HTML 269Page - Microchip Technology LAN9252/ML Datasheet HTML 270Page - Microchip Technology LAN9252/ML Datasheet HTML 271Page - Microchip Technology LAN9252/ML Datasheet HTML 272Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 268 / 329 page
background image
LAN9252
DS00001909A-page 268
 2015 Microchip Technology Inc.
Note 34:
Write access depends upon the assignment of the MI interface (ECAT/PDI).
Note:
Port 3 is not used.
12.14.59 FMMU[2:0] REGISTERS
The device includes 3 FMMUs. Each FMMU is described in 16 Bytes, starting at 0600h. Table 12-16 details the base
address for each FMMU. The subsequent FMMU registers will be referenced as an offset from these various base
addresses. The variable “x” is used in the following descriptions to represent FMMUs 0 through 2.
12.14.59.1 FMMUx Logical Start Address Register
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
2
Port x Link Status Error
0:
No Error
1:
Link Error, Link Inhibited
RO
RO
0b
1
Port x Link Status
(100 Mbit/s, Full-Duplex, Auto-negotiation)
0:
No Link
1:
Link Detected
RO
RO
0b
0
Port x Physical Link
(PHY Status Register 1.2)
0:
No Physical Link
1:
Physical Link Detected
RO
RO
0b
TABLE 12-16: FMMU X BASE ADDRESSES
FMMU
Base Address
0
0600h
1
0610h
2
0620h
Offset:
FMMUx Base Address +0h-3h
Size:
32 bits
Bits
Description
ECAT
Type
PDI
Type
Default
31:0
Logical Start Address
Logical start address within the EtherCAT address space.
R/W
RO
00000000h
Bits
Description
ECAT
Type
PDI
Type
Default



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com