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LAN9252/ML データシート(PDF) 283 Page - Microchip Technology

部品番号 LAN9252/ML
部品情報  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252/ML データシート(HTML) 283 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 283
LAN9252
12.14.74 ACTIVATION REGISTER
Note:
Writes to this register depend on the Sync Out Unit Control bit of the Cyclic Unit Control Register.
Offset:
0981h
Size:
8 bits
Bits
Description
ECAT
Type
PDI
Type
Default
7
SyncSignal Debug Pulse (Vasili Bit)
0:
Deactivated
1:
Immediately generate a single debug ping on SYNC0 and
SYNC1 according to bits 2 and 1 of this register.
R/W
R/W
0b
6
Near Future Configuration (approx.)
0:
1/2 DC width future (231 ns or 263 ns)
1:
2.1 sec future (231 ns)
R/W
R/W
0b
5
Start Time Plausibility Check
0:
Disabled. SyncSignal generation if Start Time is reached.
1:
Immediate SyncSignal generation if Start Time is outside Near
Future Configuration (approx.).
R/W
R/W
0b
4
Extension of Start Time Cyclic Operation
(Start Time Cyclic Operation Register)
0:
No extension
1:
Extend 32-bit written Start Time to 64-bit
R/W
R/W
0b
3
Auto-activation
(By writing Start Time Cyclic Operation Register)
0:
Disabled
1:
Auto-activation enabled. Sync Out Unit Activation is set auto-
matically after Start Time is written.
R/W
R/W
0b
2
SYNC1 Generation
0:
Deactivated
1:
SYNC1 pulse is generated
R/W
R/W
0b
1
SYNC0 Generation
0:
Deactivated
1:
SYNC0 pulse is generated
R/W
R/W
0b
0
Sync Out Unit Activation
0:
Deactivated
1:
Activated
Note:
Write 1 after Start Time is written
R/W
R/W
0b



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