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LAN9252/ML データシート(PDF) 304 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 304 Page - Microchip Technology |
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304 / 329 page  LAN9252 DS00001909A-page 304 2015 Microchip Technology Inc. 16.1.3 HARDWARE CONFIGURATION REGISTER (HW_CFG) This register allows the configuration of various hardware features. Note: This register can be read while the device is in the reset or not ready / power savings states without leaving the host interface in an intermediate state. If the host interface is in a reset state, returned data may be invalid. Note: It is not necessary to read all fours BYTEs of this register. DWORD access rules do not apply to this register. Offset: 074h Size: 32 bits Bits Description Type Default 31:28 RESERVED RO - 27 Device Ready (READY) When set, this bit indicates that the device is ready to be accessed. Upon power-up, RST# reset, return from power savings states, EtherCAT chip level or module level reset, or digital reset, the host processor may interrogate this field as an indication that the device has stabilized and is fully active. This rising edge of this bit will assert the Device Ready (READY) bit in the Interrupt Status Register (INT_STS) and can cause an interrupt if enabled. Note: With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and RESET_CTL registers, read access to any internal resources is forbidden while the READY bit is cleared. Writes to any address are invalid until this bit is set. Note: This bit is identical to bit 0 of the Power Management Control Register (PMT_CTRL). RO 0b 26 RESERVED RO - 25 RESERVED RO - 24:22 RESERVED RO - 21:16 RESERVED RO - 15:14 RESERVED RO - 13:12 RESERVED RO - 11:0 RESERVED RO - |
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