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LAN9252/ML データシート(PDF) 306 Page - Microchip Technology

部品番号 LAN9252/ML
部品情報  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252/ML データシート(HTML) 306 Page - Microchip Technology

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LAN9252
DS00001909A-page 306
 2015 Microchip Technology Inc.
17.1.1
JTAG TIMING REQUIREMENTS
This section specifies the JTAG timing of the device.
Note:
Timing values are with respect to an equivalent test load of 25 pF.
FIGURE 17-1:
JTAG TIMING
TABLE 17-2:
JTAG TIMING VALUES
Symbol
Description
Min
Max
Units
Notes
ttckp
TCK clock period
40
ns
ttckhl
TCK clock high/low time
ttckp*0.4
ttckp*0.6
ns
tsu
TDI, TMS setup to TCK rising edge
5
ns
th
TDI, TMS hold from TCK rising edge
5
ns
tdov
TDO output valid from TCK falling edge
15
ns
tdoinvld
TDO output invalid from TCK falling edge
0
ns
TCK (Input)
TDI, TMS (Inputs)
ttckhl
ttckp
ttckhl
tsu
th
tdov
TDO (Output)
tdoinvld



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