LAN9252VSLASHML datasheet(23/329 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001909A-page 23

LAN9252

Data

D[15:0]

VIS/VO8

These pins are the host bus data bus for non-multi-

plexed address mode.

In 8-bit data mode, bits 15-8 are not used and their

input and output drivers are disabled.

Address & Data

AD[15:0]

VIS/VO8

These pins are the host bus address / data bus for

multiplexed address mode.

Bits 15-8 provide the upper byte of address for sin-

gle phase multiplexed address mode.

Bits 7-0 provide the lower byte of address for single

phase multiplexed address mode and both bytes of

address for dual phase multiplexed address mode.

In 8-bit data dual phase multiplexed address mode,

bits 15-8 are not used and their input and output

drivers are disabled.

Address Latch

Enable High

ALEHI

VIS

This pin indicates the address phase for multiplexed

address modes. It is used to load the higher

address byte in dual phase multiplexed address

mode.

Normally active low (address saved on rising edge),

the polarity can be changed via the HBI ALE Polar-

ity bit of the PDI Configuration Register (HBI

Modes).

Address Latch

Enable Low

ALELO

VIS

This pin indicates the address phase for multiplexed

address modes. It is used to load both address

bytes in single phase multiplexed address mode

and the lower address byte in dual phase multi-

plexed address mode.

Normally active low (address saved on rising edge),

the polarity can be changed via the HBI ALE Polar-

ity bit of the PDI Configuration Register (HBI

Modes).

TABLE 3-7:

HOST BUS PIN DESCRIPTIONS (CONTINUED)

Num

Pins

Name

Symbol

Buffer

Type

Description

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