LAN9252VSLASHML datasheet(100/329 Pages) MICROCHIP

100 / 329 page

LAN9252

DS00001909A-page 100

 2015 Microchip Technology Inc.

9.5.7.2

Write Timing Requirements

If RD and WR signaling is used, a host write cycle begins when WR is asserted with CS active. The cycle ends when

WR is de-asserted. CS maybe asserted and de-asserted along with WR but not during WR active.

Alternatively, if RD_WR and ENB signaling is used, a host write cycle begins when ENB is asserted with CS active and

RD_WR indicating a write. The cycle ends when ENB is de-asserted. CS maybe asserted and de-asserted along with

ENB but not during ENB active.

Please refer to Section 9.5.6, "Indexed Address Mode Functional Timing Diagrams," on page 90 for functional descrip-

tions.

FIGURE 9-37:

INDEXED ADDRESSING WRITE CYCLE TIMING

TABLE 9-5:

INDEXED ADDRESSING WRITE CYCLE TIMING VALUES

Symbol

Description

Min

Typ

Max

Units

tcswr

CS Setup to WR or ENB Active

twrcs

CS Hold from WR or ENB Inactive

tas

Address Setup to WR or ENB Active

tah

Address Hold from to WR or ENB Inactive

trdwrs

RD_WR Setup to ENB Active

Note 16

5ns

trdwrh

RD_WR Hold from ENB Inactive

Note 16

5ns

tds

Data Setup to WR or ENB Inactive

tdh

Data Hold from WR or ENB Inactive

twr

WR or ENB Active Time

ENB, WR

D[7:0]

twr

twrwr

twrrd

twrcyc

RD_WR

trdwrh

tcswr

twrcs

tds

tdh

D[15:8]

A[4:0]

tas

tah

trdwrs

LAN9252V/ML データシート(PDF) 100 Page - Microchip Technology

LAN9252V/ML データシート(HTML) 100 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード