SII3531A datasheet(4/81 Pages) SILICONIMAGE

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PCI Express to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

SiI-DS-0208-C

6.1

PCI Configuration Space ........................................................................................................................ 43

6.1.1

Device ID – Vendor ID........................................................................................................................................44

6.1.2

PCI Status – PCI Command...............................................................................................................................44

6.1.3

PCI Class Code – Revision ID............................................................................................................................45

6.1.4

BIST – Header Type – Latency Timer – Cache Line Size ..................................................................................45

6.1.5

Base Address Register 0....................................................................................................................................45

6.1.6

Base Address Register 1....................................................................................................................................46

6.1.7

Base Address Register 2....................................................................................................................................46

6.1.8

Subsystem ID – Subsystem Vendor ID ..............................................................................................................46

6.1.9

Capabilities Pointer.............................................................................................................................................47

6.1.10

Max Latency – Min Grant – Interrupt Pin – Interrupt Line ...................................................................................47

6.1.11

Header Write Enable ..........................................................................................................................................47

6.1.12

Power Management Capability...........................................................................................................................48

6.1.13

Power Management Control + Status.................................................................................................................48

6.1.14

MSI Capability ....................................................................................................................................................49

6.1.15

Message Address...............................................................................................................................................49

6.1.16

MSI Message Data .............................................................................................................................................49

6.1.17

PCI Express Capability.......................................................................................................................................50

6.1.18

Device Capabilities .............................................................................................................................................50

6.1.19

Device Status and Control..................................................................................................................................51

6.1.20

Link Capabilities .................................................................................................................................................51

6.1.21

Link Status and Control ......................................................................................................................................52

6.1.22

Global Register Offset ........................................................................................................................................52

6.1.23

Global Register Data ..........................................................................................................................................52

6.1.24

Port Register Offset ............................................................................................................................................53

6.1.25

Port Register Data ..............................................................................................................................................53

6.1.26

Advanced Error Reporting Capability .................................................................................................................53

6.1.27

Uncorrectable Error Status .................................................................................................................................54

6.1.28

Uncorrectable Error Mask...................................................................................................................................54

6.1.29

Uncorrectable Error Severity ..............................................................................................................................54

6.1.30

Correctable Error Status.....................................................................................................................................55

6.1.31

Correctable Error Mask ......................................................................................................................................55

6.1.32

Advanced Error Capabilities and Control............................................................................................................55

6.1.33

Header Log.........................................................................................................................................................56

6.2

Internal Register Space – Base Address 0 ........................................................................................... 56

6.2.1

Port Slot Status Register ....................................................................................................................................57

6.2.2

Global Control ....................................................................................................................................................57

6.2.3

Global Interrupt Status........................................................................................................................................58

6.2.4

PHY Configuration..............................................................................................................................................58

6.2.5

BIST Control Register.........................................................................................................................................58

6.2.6

BIST Pattern Register.........................................................................................................................................59

6.2.7

BIST Status Register ..........................................................................................................................................59

6.2.8

MemBIST Status Register ..................................................................................................................................59

6.2.9

Configuration Register Offset .............................................................................................................................59

6.2.10

Configuration Register Data ...............................................................................................................................60

6.3

Internal Register Space – Base Address 1 ........................................................................................... 61

6.3.1

Port LRAM..........................................................................................................................................................62

6.3.2

Port Slot Status ..................................................................................................................................................63

6.3.3

Port Control Set ..................................................................................................................................................63

6.3.4

Port Status..........................................................................................................................................................64

6.3.5

Port Control Clear...............................................................................................................................................65

6.3.6

Port Interrupt Status ...........................................................................................................................................65

6.3.7

Port Interrupt Enable Set / Port Interrupt Enable Clear.......................................................................................66

6.3.8

32-bit Activation Upper Address .........................................................................................................................66

6.3.9

Port Command Execution FIFO .........................................................................................................................67

6.3.10

Port Command Error ..........................................................................................................................................67

6.3.11

Port FIS Configuration ........................................................................................................................................69

6.3.12

Port PCI Express Request FIFO Threshold........................................................................................................70

6.3.13

Port 8B/10B Decode Error Counter ....................................................................................................................70

6.3.14

Port CRC Error Counter .....................................................................................................................................71

6.3.15

Port Handshake Error Counter ...........................................................................................................................71

6.3.16

Port PHY Configuration ......................................................................................................................................71

6.3.17

Port Device Status Register ...............................................................................................................................73

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