SII3531A datasheet(71/81 Pages) SILICONIMAGE

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PCI Express to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

SiI-DS-0208-C

6.3.14 Port CRC Error Counter

Address Offset: 1044H

Access Type: Read/Write/Clear

Reset Value: 0x0000_0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

CRC Error Counter Threshold

CRC Error Counter

This register counts the number of Serial ATA CRC Errors that have occurred since last cleared.

•

Bit [31:16]: Serial ATA CRC Error Threshold (R/W). This bit field defines the count at which an interrupt will be

asserted. When the count in bits 15:0 is equal to this value, a serial ATA CRC interrupt will be latched. A

threshold value of zero disables interrupt assertion and masks the corresponding interrupt status bit in the Port

Interrupt Status register.

•

Bit [15:0]: Serial ATA CRC Error Count (R/WC). This bit field represents the count of Serial ATA CRC errors

that have occurred since this register was last written. Any write to this register will clear both the counter and

the interrupt condition. Clearing the interrupt status bit will also clear the counter. The count will not overflow.

Once this register reaches its maximum count, it will retain that count until cleared to zero by a write operation.

6.3.15 Port Handshake Error Counter

Address Offset: 1048H

Access Type: Read/Write/Clear

Reset Value: 0x0000_0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Serial ATA Handshake Error Counter Threshold

Serial ATA Handshake Error Counter

This register counts the number of Serial ATA Handshake Errors that have occurred since last cleared.

•

Bit [31:16]: Serial ATA Handshake Error Threshold (R/W). This bit field defines the count at which an interrupt

will be asserted. When the count in bits 15:0 is equal to this value, a serial ATA Handshake interrupt will be

latched. A threshold value of zero disables interrupt assertion and masks the corresponding interrupt status bit

in the Port Interrupt Status register.

•

Bit [15:0]:

Serial ATA Handshake Error Count (R/WC).

This bit field represents the count of Serial ATA

Handshake errors that have occurred since this register was last written. Any write to this register will clear both

the counter and the interrupt condition. Clearing the interrupt status bit will also clear the counter. The count will

not overflow. Once this register reaches its maximum count, it will retain that count until cleared to zero by a

write operation.

6.3.16 Port PHY Configuration

Address Offset: 1050H

Access Type: Read/Write

Reset Value: 0x0000_020C

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