X24C04 datasheet(8/18 Pages) ICMIC

8 / 18 page

X24C04

Sequential Read

Sequential Read can be initiated as either a current

address read or random access read. The first word is

transmitted as with the other modes, however, the

master now responds with an acknowledge, indicating it

requires additional data. The X24C04 continues to out- put

data for each acknowledge received. The read

operation is terminated by the master; by not responding with

an acknowledge and by issuing a stop condition.

The data output is sequential, with the data from address n

followed by the data from n + 1. The address counter

for read operations increments all address bits, allowing the

entire memory contents to be serially read during

one operation. At the end of the address space (address 511),

the counter “rolls over” to address 0 and the

X24C04 continues to output data for each acknowledge

received. Refer to Figure 9 for the address, acknowledge

and data transfer sequence.

Figure 9. Sequential Read

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24C04

SLAVE

ADDRESS

DATA n+x

DATA n

DATA n+1

DATA n+2

3839 FHD F16

Figure 10. Typical System Configuration

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

PULL-UP

RESISTORS

SDA

SCL

3839 FHD F17

X24C04 データシート(PDF) 8 Page - IC MICROSYSTEMS

X24C04 データシート(HTML) 8 Page - IC MICROSYSTEMS

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

データシートダウンロード

リンク URL

X24C04 データシート(PDF) 8 Page - IC MICROSYSTEMS

X24C04 データシート(HTML) 8 Page - IC MICROSYSTEMS

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

データシート ダウンロード

リンク URL

データシートダウンロード