L9800 datasheet(11/55 Pages) STMICROELECTRONICS

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Input/output

5.1

Control pins

The device has three pins (IN0, IN1 and IDLE) to check directly the device without using SPI.

5.2

Input pins (IN0, IN1)

The L9800 has two input pins, IN0 and IN1, by default IN0 is connected to channel 2, IN1 is connected to channel

3. It is possible through programming MAP_IN0 and MAP_IN1 (input mapping registers) to link different channels

to each input IN0 or IN1 with priority assigned to MAP_IN0. If for example, both mapping registers are written to

control the same channel, it follows the IN0 pin. The Figure 23 describes how the actuation of the channels is

managed. The channels are driven by the signals that are the OR combination between PWM_SPI_register

status, PWM generators (PWM generator output mapping status), IN0 and IN1. The STA_0 (status register)

shows the logic level of the input pins. See Section 7: Power stages for further details.

The logic level of the input pins can be monitored via the STA_0 register. In the STA_0 register, it is also possible

to monitor the status of DIS and NRES pins. The input status monitor is operative also when the device is in limp-

home mode. If one of the input pins is set to “high” and the IDLE pin is set to “low”, the device switches into limp-

home mode and activates the channel mapped by default to the input pins.

5.3

Reset pin

The NRES pin is the reset input for the device. As default, the state of the NRES pin is masked by the logic. The

user must send a specific SPI frame (setting NRES_EN or NRES_N_EN bit on the CFG_0 register) to force the

logic to take into account the state of the NRES pin. The function uses the inverse logic, if the NRES pin is low,

the device is held in an internal reset state, all output channels are disabled, and all registers are reset to their

default values. An internal pull-down holds the NRES pin asserted in case of an open pin.

Both NRES_EN and NRES_N_EN are intended to enable/disable the NRES pin.

•

When the NRES_EN bit is 1 the NRES pin is enabled; in this case, a reset event on the NRES pin puts the

registers in the default conditions, and the NRES pin in this case is disabled.

•

When the NRES_N_EN is set to 1, the NRES pin is enabled, but the reset event puts the registers in

default conditions while the NRES pin remains enabled.

5.4

DIS pin

The DIS pin is used to enable/disable the output stages. As default, the DIS pin is masked by the logic. The user

needs to send a specific SPI frame (setting the DIS_EN bit on the CFG_0 register) to force the logic to take into

account the state of the DIS pin:

•

When the DIS pin is high, all channels are disabled if the pin is not masked. An internal pull-up holds the

DIS pin asserted in case of an open pin.

•

When the DIS pin is set low, all channels are enabled based on their configuration settings. The status of

the DIS pin can be monitored reading the STA_0 register.

The DIS pin can be connected to a general purpose output pin of the microcontroller or to an alternative safety

circuit.

5.5

IDLE pin

The device enters in sleep state through IDLE pin when it is set to "low" together with IN0 and IN1. Instead if IDLE

pin is in "low" state and one of the two inputs are in "high" state the device is brought in limp-home mode.

To ensure a correct transition IDLE pin should be set at least for a time duration of tIDLEFLT_max.

Setting the IDLE pin to “low”, with both IN0 and IN1 also at “low” value, has the following consequences:

•

The SPI registers are reset to default value if IN0 and In1 are set to "low".

•

To decrease the current consumption the voltage detection circuits on VDDIO and VBATT are disabled, if

both IN0 and IN1 are set to "low". Instead if one of the two inputs is set to "high", the core is enabled with

channel 2 and channel 3 driving circuits.

•

No SPI communication is kept, the SO pin remains in "HighZ" even if NCS pin is active and the SPI

communication is not allowed.

L9800

Input/output

DS14041 - Rev 2

page 11/55

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