L99DZ80EP datasheet(8/68 Pages) STMICROELECTRONICS

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Block diagram and pin description

L99DZ80EP

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DocID18260 Rev 6

Table 2. Pin definitions and functions

Symbol

Function

57, 58

GND1

Ground: reference potential. GND1 and GND2 are internally connected.

GND1 supplies OUT1-3, GND2 supplies OUT4-6

Important: For the capability of driving the full current at the outputs, all

pins of GND must be externally connected!

17, 18,

26, 31, 32

GND2

SGND

Signal Ground: this pin is shared with GND2 pin

2, 3, 45,

46, 51, 52

VS1

Power supply voltage for power stage outputs (external reverse

protection required): for this input a ceramic capacitor as close as

possible to GND is recommended. VS1 supplies OUT1-3, OUT7-11 and

the internal VS supply, VS2 supplies OUT4-6

Important: For the capability of driving the full current at the outputs all

pins of VS must be externally connected!

11, 12, 23,

36, 37

VS2

48, 49, 50

OUT11

High-side-driver output 11: the output is built by a high-side switch and is

intended for resistive loads, hence the internal reverse diode from GND

to the output is missing. For ESD reason a diode to GND is present but

the energy which can be dissipated is limited. The High-side driver is a

power DMOS transistor with an internal parasitic reverse diode from the

output to VS (bulk-drain-diode). The output is overcurrent and open load

protected.

Important: For the capability of driving the full current at the outputs all

pins of OUT11 must be externally connected!

59, 60

OUT1

Half-bridge outputs 1,2,3,4,5,6: the output is built by a high side and a low

side switch, which are internally connected. The output stage of both

switches is a power DMOS transistor. Each driver has an internal

parasitic reverse diode (bulk-drain-diode: high side driver from output to

VS, low side driver from GND to output). This output is over current and

open load protected.

OUT2

OUT3

19, 20,

21, 22

OUT4

27, 28,

29, 30

OUT5

24, 25

OUT6

Serial data output: the diagnosis data is available via the SPI and this

3-state-output. The output remains in 3-state, if the chip is not selected by

the input CSN (CSN = high).

Current monitor output: depending on the selected multiplexer bits of the

Control Register this output sources an image of the instant current

through the corresponding high side driver with a fixed ratio.

CSN

Chip-Select-Not input: this input is low active and requires CMOS logic

levels. The serial data transfer between the device and the micro

controller is enabled by pulling the input CSN to low level.

Serial data input: the input requires CMOS logic levels and receives serial

data from the microcontroller. The data is a 24 bit control word and the

most significant bit (MSB, bit 23) is transferred first.

CLK

Serial clock input: this input controls the internal shift register of the SPI

and requires CMOS logic levels.

DIR

Direction Input: this input controls the H-Bridge Drivers

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