STM32H533CE datasheet(31/231 Pages) STMICROELECTRONICS

31 / 231 page

DS14539 Rev 1

31/231

STM32H533xx

Functional overview

3.10.5

PWR TrustZone security

When the TrustZone security is activated by the TZEN option bit, the PWR is switched in

TrustZone security mode.

The PWR TrustZone security secures the following configuration:

•

Low-power mode

•

Wake-up (WKUP) pins

•

Voltage detection and monitoring

•

VBAT mode

Some of the PWR configuration bits security is defined by the security of other peripherals:

•

The voltage scaling (VOS) configuration is secure when the system clock selection is

secure in RCC.

•

The I/O pull-up/pull-down in Standby mode configuration is secure when the

corresponding GPIO is secure.

•

The backup domain write protection is secure when the RTC is secure.

3.11

Peripheral interconnect matrix

Several peripherals have direct connections between them, that allow autonomous

communication between them and support the saving of CPU resources (thus power supply

consumption). In addition, these hardware connections allow fast and predictable latency.

Depending on the peripherals, these interconnections can operate in Run and Sleep modes.

3.12

Reset and clock controller (RCC)

The clock controller distributes the clocks coming from the different oscillators to the core

and to the peripherals. It also manages the clock gating for low-power modes and ensures

the clock robustness. It features:

•

Clock prescaler: in order to get the best trade-off between speed and current

consumption, the clock frequency to the CPU and peripherals can be adjusted by a

programmable prescaler.

•

Clock security system: clock sources can be changed safely on the fly in Run mode

through a configuration register.

•

Clock management: in order to reduce the power consumption, the clock controller

can stop the clock to the core, individual peripherals or memory.

•

System clock source: four different clock sources can be used to drive the master

clock SYSCLK:

–

4 to 50 MHz high-speed external crystal or ceramic resonator (HSE), can supply a

PLL. The HSE can also be configured in bypass mode for an external clock.

–

64 MHz high-speed internal RC oscillator (HSI), trimmable by software, can

supply a PLL.

–

4 MHz low-power internal oscillator (CSI), trimmable by software, can supply a

PLL.

–

System PLL, which can be fed by HSE, HSI or CSI, with a maximum frequency at

250 MHz.

STM32H533CE データシート(PDF) 31 Page - STMicroelectronics

STM32H533CE データシート(HTML) 31 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード