STM32H533CE datasheet(42/231 Pages) STMICROELECTRONICS

42 / 231 page

Functional overview

STM32H533xx

42/231

DS14539 Rev 1

3.29

Secure advanced encryption standard hardware accelerator

(SAES) and encryption standard hardware accelerator (AES)

The devices embed two AES accelerators: SAES and AES. The SAES with hardware

unique key embeds protection against differential power analysis (DPA) and related side

channel attacks. The SAES can share its current key register information with the faster

AES using a dedicated hardware bus.

The SAES and the AES can be used to both encrypt and decrypt data using the AES

algorithm. It is a fully compliant implementation of the advanced encryption standard (AES)

as defined by Federal Information Processing Standards Publication (FIPS PUB 197, Nov

2001).

Multiple chaining modes are supported for key sizes of 128 or 256 bits. ECB, CBC, CTR,

CCM, GCM and GMAC chaining are supported by the AES and SAES.

SAES and AES support DMA single transfers for incoming and outgoing data (two DMA

channels required).

The SAES supports the selection of all the following key sources, while the AES support

only the first:

•

256-bit software key, written by the application in the key registers (write only)

•

256-bit derived by hardware secure key management.

The SAES and AES peripherals support:

•

Compliant implementation of standard NIST Special Publication 197, Advanced

Encryption Standard (AES) and Special Publication 800-38A, Recommendation for

Block Cipher Modes of Operation

•

128-bit data block processing

•

Support for cipher keys length of 128-bit and 256-bit

•

Encryption and decryption with multiple chaining modes:

–

Electronic codebook (ECB) mode

–

Cipher block chaining (CBC) mode

–

Counter (CTR) mode

–

Galois counter mode (GCM)

–

Galois message authentication code (GMAC) mode

–

Counter with CBC-MAC (CCM) mode

•

528 or 743 clock cycle latency in ECB encryption mode for SAES processing one

128-bit block of data with, respectively, 128-bit or 256-bit key

•

51 or 75 clock cycle latency in ECB encryption mode for AES processing one 128-bit

block of data with, respectively, 128-bit or 256-bit key

•

Integrated round key scheduler to compute the last round key for AES ECB/CBC

decryption

•

256-bit register for storing the cryptographic key (four 32-bit registers), with key

atomicity enforcement

•

128-bit registers for storing initialization vectors (four 32-bit registers)

•

One 32-bit INPUT buffer and one 32-bit OUTPUT buffer

•

Automatic data flow control with support of single-transfer direct memory access (DMA)

using two channels (one for incoming data, one for processed data)

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