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GD32H757VMT7 データシート(PDF) 113 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32H757VMT7 データシート(HTML) 113 Page - GigaDevice Semiconductor (Beijing) Inc. |
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113 / 151 page  GD32H757xx Datasheet 112 Symbol Parameter Conditions Min Typ Max Unit VAIN Conversion voltage range — 0 — VREF P V VCMIV Common mode input voltage — VREFP/ 2- 10% VREFP/ 2 VREF P /2- 10% RAIN External input impedance Resolution = 12 bits — — 109 k Ω Resolution = 10 bits — — 128 Resolution = 8 bits — — 153 Resolution = 6 bits — — 192 RADC Internal resistance — — 250 — Ω CADC Input capacitanc e — — 7.5 — pF tSTAB ADC Power-up time — - 1 — μs tOFF_ CAL Offset calibration time — 46 — — 1/fADC ts Sampling time — 2.5 — 640. 5 1/fADC tCONV Total conversion time (including sampling time) Resolution = N bits 3+N — — 1/ fADC (1) Value guaranteed by design, not 100% tested in production. (2) Depending on the package, VREFP can be internally connected to VDDA and VREFN to VSSA. (3) VREFP should always be equal to or less than VDDA, especially during power up. Table 4-36. ADC RAIN max for fADC = 80 MHz (12-bit ADC) (1)(2) Resolution Sampling cycles @ 80 MHz RAIN max (kΩ) 12 bits 2.5 0.17 6.5 0.86 12.5 1.89 24.5 3.95 47.5 7.90 92.5 15.6 247.5 42.2 |
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