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ST7L05 データシート(PDF) 80 Page - STMicroelectronics |
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ST7L05 データシート(HTML) 80 Page - STMicroelectronics |
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80 / 104 page ![]() ST7L05, ST7L09 80/104 13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC and TA. 13.5.1 General Timings Notes: 1. Guaranteed by Design. Not tested in production. 2. Data based on typical application software. 3. Time measured between interrupt event and interrupt vector fetch. Dtc(INST) is the number of tCPU cycles needed to fin- ish the current instruction execution. Symbol Parameter1) Conditions Min Typ2) Max Unit tc(INST) Instruction cycle time fCPU =8 MHz 23 12 tCPU 250 375 1500 ns tv(IT) Interrupt reaction time3) tv(IT) = ∆tc(INST) + 10 fCPU =8 MHz 10 22 tCPU 1.25 2.75 µs 1 |
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