M7020R datasheet(33/150 Pages) STMICROELECTRONICS

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M7020R

Table 20. READ Address Format for Internal Registers

Table 21. READ Address Format for Data and Mask Arrays

WRITE COMMAND

The WRITE can be a single write of a data array,

mask array, register, or external SRAM location

(CMD[2] =

0). It can

burst WRITE

(CMD[2] = 1) using an internal auto-incrementing

address register (WBURADR) of the data array or

mask array locations. A single-location WRITE is a

three-cycle operation, shown in Figure 17, page

34. The burst WRITE adds one extra cycle for

each successive WRITE.

The WRITE operation sequence is as follows:

– Cycle 1A: The host ASIC applies the WRITE In-

struction on the CMD[1:0] (CMD[2] = 0), using

CMDV=1 and the address supplied on the DQ

Bus, as shown in Table 22, page 35. The host

ASIC also supplies the index to the global mask

mask array location in CMD[5:3]. For SRAM

WRITEs, the host ASIC must supply the

SADR[21:20] on CMD[8:6]. The host ASIC sets

CMD[9] to '0' for the normal WRITE.

– Cycle 1B: The host ASIC continues to apply the

WRITE

Instruction

the

CMD[1:0]

(CMD[2] = 0), using CMDV = 1 and the address

supplied on the DQ Bus. The host ASIC contin-

ues to supply the global mask register index to

mask the WRITE to the data or mask array loca-

tions in CMD[5:3]. The host ASIC selects the

device where ID[4:0] matches the DQ[25:21]

lines, or it selects all the devices when

DQ[25:21] = 11111.

– Cycle 2: The host ASIC drives the DQ[67:0]

with the data to be written to the data array,

mask array, external SRAM, or register location

of the selected device.

– Cycle 3: Idle cycle. At the termination of this cy-

cle, another operation can begin.

Note: The latency of the SRAM WRITE will be

different than the one described above (see

SRAM PIO Access, page 126).

The burst WRITE operation lasts for n + 2 CLK cy-

cles (where n signifies the number of accesses in

the burst as specified in the BLEN field of the

WBURREG register, please see Figure 18, page

35).

This operation assumes that the host ASIC has

programmed the WBURREG with the starting ad-

dress (ADR) and the length of transfer (BLEN) be-

fore initiating the burst write command (see Table

24, page 36 for format). The sequence is as fol-

lows:

– Cycle 1A: The host ASIC applies the WRITE In-

struction on the CMD[1:0] (CMD[2] = 1), using

CMDV = 1 and the address supplied on the DQ

Bus, as shown in Table 24, page 36. The host

ASIC also supplies the index to the global mask

ray locations in CMD[5:3].

– Cycle 1B: The host ASIC continues to apply the

WRITE

Instruction

the

CMD[1:0]

(CMD[2] = 0), using CMDV = 1 and the address

supplied on the DQ Bus. The host ASIC contin-

ues to supply the global mask register index to

mask the WRITE to the data or mask array loca-

tions in CMD[5:3]. The host ASIC selects the

device where ID[4:0] matches the DQ[25:21]

lines, or it selects all the devices when

DQ[25:21] = 11111.

DQ[67:26]

DQ[25:21]

DQ[20:19]

DQ[18:6]

DQ[5:0]

Reserved

11: Register

Reserved

DQ[67:26]

DQ[25:21]

DQ[20:19]

DQ[18:15]

DQ[14:0]

Reserved

00: Data Array

Reserved

Do not care. These 15 bits come from the internal

access.

Reserved

01: Mask

Array

Reserved

Do not care. These 16 bits come from the internal

access.

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