M7020R datasheet(40/150 Pages) STMICROELECTRONICS

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M7020R

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68-bit SEARCH on Tables Configured as x68 Using up to Eight M7020R Devices

The hardware diagram of the search subsystem of

eight devices is shown in Figure 22, page 41. The

following are the parameters programmed into the

eight devices:

– First seven devices (device 0–6):

CFG = 00000000, TLSZ = 01, HLAT = 010,

LRAM = 0, and LDEV = 0.

– Eighth device (device 7):

CFG = 00000000, TLSZ = 01, HLAT = 010,

LRAM = 1, and LDEV = 1.

Note: All eight devices must be programmed with

the same values for TLSZ and HLAT. Only the last

device in the table (Device 7 in this case) must be

programmed with LRAM = 1 and LDEV = 1. All

other upstream devices (Devices 0 through 6 in

this case) must be programmed with LRAM = 0

and LDEV = 0.

Figure 24, page 43 shows the timing diagram for a

SEARCH command in the 68-bit-configured table

of eight devices for Device 0. Figure 25, page 44

shows the timing diagram for a SEARCH com-

mand in the 68-bit-configured table of eight devic-

es for Device 1. Figure 26, page 45 shows the

timing diagram for a SEARCH command in the

68-bit-configured table of eight devices for Device

7 (the last device in this specific table). For these

timing diagrams four 68-bit searches are per-

formed sequentially. HIT/MISS assumptions were

made as shown below in Table 27.

The sequence of operation for a 68-bit SEARCH

command is as follows:]

– Cycle A: The host ASIC drives CMDV high and

applies the SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] must be driven with

the index to the global mask register pair for use

in the SEARCH operation. CMD[8:7] signals

must be driven with the same bits that will be

driven on SADR[23:21] by this device if it has a

hit. DQ[67:0] must be driven with the 68-bit data

to be compared. The CMD[2] signal must be

driven to Logic '0.'

– Cycle B: The host ASIC continues to drive

CMDV high and applies the SEARCH command

('10') on CMD[1:0]. CMD[5:2] must be driven by

the index of the comparand register pair for stor-

ing the 136-bit word presented on the DQ Bus

during Cycles A and B. CMD[8:6] signals must

be driven with the index of the SSR that will be

used for storing the address of the matching en-

try and the Hit Flag (see SEARCH-Successful

Registers (SSR[0:7]), page 23). The DQ[67:0]

continues to carry the 68-bit data to be com-

pared.

Note: For 68-bit searches, the host ASIC must

supply the same data on DQ[67:0] during both

Cycles A and B. The even and odd pair of

GMRs selected for the comparison must be pro-

grammed with the same value.

The logical 68-bit SEARCH operation is shown in

Figure 23, page 42. The entire table with eight de-

vices of 68-bit entries is compared to a 68-bit word

K (presented on the DQ Bus in both Cycles A and

B of the command) using the GMR and the local

mask bits. The effective GMR is the 68-bit word

specified by the identical value in both even and

odd GMR pairs in each of the eight devices and

selected by the GMR Index in the command’s Cy-

cle A. The 68-bit word K (presented on the DQ Bus

in both Cycles A and B of the command) is also

stored in both even and odd comparand register

pairs (selected by the Comparand Register Index

in command Cycle B) in each of the eight devices.

In the x68 configuration, only the even comparand

command in one of the devices (only the first non-

full device). The word K (presented on the DQ Bus

in both Cycles A and B of the command) is com-

pared with each entry in the table starting at loca-

tion “0.” The first matching entry’s location

address, “L,” is the winning address that is driven

as part of the SRAM address on the SADR[21:0]

lines (see SRAM ADDRESSING, page 126). The

global winning device will drive the bus in a specif-

ic cycle. On a global miss cycle the device with

LRAM = 1 (default driving device for the SRAM

Bus) and LDEV = 1 (default driving device for SSF

and SSV signals) will be the default driver for such

missed cycles.

The SEARCH command is a pipelined operation

and executes a search at half the rate of the fre-

quency of CLK2X for 72-bit searches in x68-con-

figured tables. The latency of SADR, CE_L,

ALE_L, WE_L, SSV, and SSF from the 68-bit

SEARCH command cycle (two CLK2X cycles) is

shown in Table 28, page 46

The latency of the search from command to SRAM

access cycle is 5 for up to eight devices in the table

(TLSZ = 01). SSV and SSF also shift further to the

right for different values of HLAT, as specified in

Table 29, page 46.

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