M7020R datasheet(36/150 Pages) STMICROELECTRONICS

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M7020R

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Table 23. WRITE Address Format for Internal Registers

Table 24. WRITE Address Format for Data and Mask Array (Burst Write)

SEARCH COMMAND

The M7020R (Silicon) Search Engine can be con-

figured in ten ways:

– 68-bit SEARCH on tables configured as x68

using one device

– 68-bit SEARCH on tables configured as x68

using up to 8 devices

– 68-bit SEARCH on tables configured as x68

using up to 31 devices

– 136-bit SEARCH on tables configured as

x136 using one device

– 136-bit SEARCH on tables configured as

x136 using up to 8 devices

– 136-bit SEARCH on tables configured as

x136 using up to 31 devices

– 272-bit SEARCH on tables configured as

x272 using one devices

– 272-bit SEARCH on tables configured as

x272 using up to 8 devices

– 272-bit SEARCH on tables configured as

x272 using up to 31 devices

– Mixed-sizes on tables configured with differ-

ent widths using an M7020R

68-bit Configuration with Single Device

The hardware diagram of the search subsystem of

a single device is shown in Figure 19. Figure 20,

page 38 shows the timing diagram for a SEARCH

operation in the 68-bit configuration (CFG =

00000000) for one set of parameters. This illustra-

tion assumes that the host ASIC has programmed

TLSZ to '00,' HLAT to '000,' LRAM to '1,' and LDEV

to '1' in the command register.

The following is the sequence of operations for a

single 68-bit SEARCH command.

– Cycle A: The host ASIC drives CMDV high and

applies the SEARCH command code ('10') on

CMD[1:0] signals. CMD[5:3] must be driven with

the index to the global mask register pair for use

in the SEARCH operation. CMD[8:7] signals

must be driven with the same bits that will be

driven on SADR[21:20] by this device if it has a

hit. DQ[67:0] must be driven with the 68-bit data

to be compared. The CMD[2] signal must be

driven to Logic '0.'

– Cycle B: The host ASIC continues to drive

CMDV high and applies the SEARCH command

('10') on CMD[1:0]. CMD[5:2] must be driven by

the index of the comparand register pair for stor-

ing the 136-bit word presented on the DQ Bus

during Cycles A and B. CMD[8:6] signals must

be driven with the index of the SSR that will be

used for storing the address of the matching en-

try and the Hit Flag (see SEARCH-Successful

Registers (SSR[0:7]), page 23). The DQ[67:0]

continues to carry the 68-bit data to be com-

pared.

Note: In the 68-bit configuration, the host ASIC

must supply the same data on DQ[67:0] during

both Cycles A and B. The even and odd pair of

GMRs selected for the comparison must be pro-

grammed with the same value.

DQ[67:26]

DQ[25:21]

DQ[20:19]

DQ[18:6]

DQ[5:0]

Reserved

11: Register

Reserved

[67:26]

[25:21]

[20:19]

[18:15]

[14:0]

Reserved

00: Data array

Reserved

Don’t care. These 15 bits come from the internal

access.

Reserved

01: Mask

array

Reserved

Don’t care. These 15 bits come from the internal

access.

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