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CHR71000 データシート(PDF) 45 Page - ams-OSRAM AG |
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CHR71000 データシート(HTML) 45 Page - ams-OSRAM AG |
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45 / 54 page ![]() CHR71000 Register description Datasheet • PUBLIC • Document Feedback DS000427 • v2-01 • 2026-Mar-18 45 / 54 / Addr Bits Name Description Default Recommended 87 [3:0] reg_offset_14[11:8] MSB of DAC offset 8 8 87 [7:4] reg_offset_15[11:8] MSB of DAC offset 8 8 88 [5:0] reg_dac_high[5:0] Internal DAC high setting 48 52 89 [5:0] reg_dac_low[5:0] Internal DAC low setting 16 12 90 [5:0] reg_rblank_ref[5:0] Internal reference voltage setting 32 26 91 [5:0] reg_clamp[5:0] Clamping circuit in output stage 63 63 92 [7:0] reg_stby[7:0] Standby register 0 0 93 [3:0] reg_clk_delay[3:0] Clock delay for sample signal output stage 5 0 [4] reg_prebuf_en Mux buffer before output stage 1 0 [5] reg_bgap_on Internal bandgap reference 1 1 [6] reg_separate_mux Separate multiplexer bus lines 1 1 94 [3:0] reg_pw_ctr_coldriv[3:0] Current bias column drivers 8 14 [7:4] reg_pw_ctr_pixcds[3:0] Current bias column amp CDS stage 8 14 95 [3:0] reg_pw_ctr_colbias[3:0] Current bias column bus (ctu) 8 0 [7:4] reg_pw_ctr_colpc[3:0] Current bias column bus (precharge) 10 15 96 [3:0] reg_pw_ctr_driv[3:0] Current of the output buffers 8 1(1) [7:4] reg_pw_ctr_pga[3:0] Current bias output amp CDS/PGA stage 8 8(2) 97 [3:0] reg_clk_delay_clk_smp[3:0] Delay of clk_smp (3) 125 [0] reg_latch_temp_data Temperature sensor latch 126 [7:0] reg_temperature[7:0] Temperature sensor read out 0 0 127 [7:0] reg_temperature[15:8] Temperature sensor read out 0 0 (1) System dependent: this depends on the output load of the sensor in the camera, the higher the load, the higher this value should be at the expense of power consumption. Increasing the current of the output buffers will increase the slew rate of the outputs. This can be used to adapt the sensor outputs to the receiver systems input capacitance. (2) Testing was done with setting 14, setting 1 shows no visible degradation. (3) This register can be used to fine-tune the output clock delay for your specific receiver (ADC) to the data. The delay can be set between 0° - 180°. The registers reg_revision[7:0] and reg_temperature[15:0] are read-only registers. A write operation to one of these registers will not change their contents. All addresses that are not mentioned in this list are reserved and may not be overwritten. |
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