RZSLASHT2M datasheet(3/128 Pages) RENESAS

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Table 1.3

System

Feature

Functional description

Operating modes

The operating mode can be selected from the following seven boot modes:

● xSPI0 boot mode (CS0 × 1 boot Serial Flash)

● xSPI0 boot mode (CS0 × 8 boot Serial Flash)

● 16-bit bus boot mode (CS0 NOR Flash)

● 32-bit bus boot mode (CS0 NOR Flash)

● xSPI1 boot mode (CS0 × 1 boot Serial Flash)

● SCI boot mode

● USB boot mode

Clock generation circuit

● The input clock can be selected from an external clock or external resonator.

● Detection of input clock oscillation stopping

● The following clocks are generated:

– CPU0 clock: System clock x1, x2 or x4

– CPU1 clock: System clock x1, x2 or x4

– System clock: 150 or 200 MHz

– High-speed peripheral module clock: 150 or 200 MHz

– Middle-speed peripheral module clock: 75 or 100 MHz

– Low-speed peripheral module clock: 37.5 or 50 MHz

– ADC clock in the 12-bit A/D converter: 18.75 or 25 MHz

– External bus clock: 100 MHz (max.)

– Low-speed on-chip oscillator: 240 kHz (fixed)

Reset

RES# pin reset, software reset, error reset, CPU0 software reset, CPU1 software reset

Low-power consumption function

● Standby mode (Cortex-R52)

● Module stop function

Interrupt controller (ICU)

● Connect an interrupt to the GIC (Generic Interrupt Controller) for Cortex-R52 CPU0 and

CPU1

● Connect an activating trigger to the DMAC and ELC

● Peripheral function interrupts: 394 sources

● External interrupts: 16 sources (IRQ0 to IRQ15 pins)

● Software interrupts: 8 sources

● Non-maskable interrupts: 1 sources

● 32 levels specifiable for the order of priority in the GIC

Bus state controller (BSC)

● The external address space is divided into four areas (CS0, CS2, CS3, and CS5) for

management.

● The following features are configurable for each area independently:

Bus size (8, 16, or 32 bits): Available sizes depend on the area. Number of access wait

cycles (different wait cycles can be specified for read and write access cycles in some

areas). Idle wait cycle insertion (between same area access cycles or different area access

cycles). Specifying the memory to be connected to each area enables direct connection

to SRAM, SRAM with byte selection, SDRAM, and burst ROM (clocked synchronous or

asynchronous). The address/data multiplexed I/O (MPX) interface is also available.

● Outputs a chip select signal (CS0# to CS5#) according to the target area (CS assert or

negate timing can be selected by software).

● Connectable memory type for each area

CS0: SRAM, burst ROM

CS2: SRAM

CS2 + CS3: SRAM, SDRAM (CS2 only for SDRAM is not supported)

CS3: SRAM, SDRAM

CS5: SRAM, MPX-IO

● SDRAM refresh

Auto refresh or self-refresh mode selectable

● SDRAM burst access

Table 1.4

Direct memory access

Feature

Functional description

Direct memory access controller

(DMAC)

● 2 units (16 channels each unit)

● Transfer modes: Single transfer mode and block transfer mode

● Transfer size

- Unit 0: 1/2/4/8/16/32/64 bytes

- Unit 1: 1/2/4/8/16/32 bytes

● Activation sources: Software trigger, external DMA requests (DREQ), external interrupts,

and interrupt requests from peripheral functions

RZ/T2M Datasheet

1. Overview

R01DS0383EJ0130 Rev.1.30

Mar 13, 2026

Page 3 of 128

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