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RZ/T2M データシート(PDF) 91 Page - Renesas Technology Corp |
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RZ/T2M データシート(HTML) 91 Page - Renesas Technology Corp |
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91 / 128 page ![]() Output stopping signal from GPT*1 GPT PWM output pins Outputs disabled tPOEGDO Note 1. GPTn.GTST.DTEF (dead time error flag), GPTn.GTST.OABLF (simultaneous low out flag), or GPTn.GTST.OABHF (simultaneous high output flag) Figure 2.51 Output disable time for POEG in response to detection of the output stopping signal from GPT POEGmGn.SSF bit (m = 0 to 2, n = A to D) GPT PWM output pins Outputs disabled tPOEGDS Figure 2.52 Output disable time for POEG in response to the register setting GPT PWM output pins Oscillation stop detection signal (internal signal) Main clock Outputs disabled tPOEGDOS Figure 2.53 Output disable time for POEG in response to the oscillation stop detection 2.5.5.7 A/D Converter Trigger Timing Table 2.31 A/D converter trigger timing Parameter Symbol Min. Max. Unit*1 Reference figure A/D converter A/D converter trigger input pulse width ADTRG0#, ADTRG1# tTRGW 1.5 — tPADCcyc Figure 2.54 Note 1. tPADCcyc: PCLKADC cycle PCLKADC tTRGW ADTRG0# ADTRG1# Figure 2.54 A/D converter trigger input timing (ADTRG0#, ADTRG1#) RZ/T2M Datasheet 2. Electrical Characteristics R01DS0383EJ0130 Rev.1.30 Mar 13, 2026 Page 91 of 128 |
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