RZSLASHN2L datasheet(74/128 Pages) RENESAS

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2.5.5.4

POE3 Timing

Table 2.28

POE3 timing

Parameter

Symbol

Min.

Max.

Unit*1

Reference figure

POE3

POEn# input pulse width

tPOEW

2.5

—

tPHcyc

Figure 2.42

Output disable time Transition of the POEn#

signal level

tPOEDI

—

5 × PCLKH

+ 0.1

µs

Figure 2.43

Simultaneous conduction

of output pins

tPOEDO

—

3 × PCLKH

+ 0.1

µs

Figure 2.44

tPOEDS

—

PCLKH +

0.1

µs

Figure 2.45

Oscillation stop detection

tPOEDOS

—

µs

Figure 2.46

Note 1. tPHcyc: PCLKH cycle

PCLKH

tPOEW

POEn# input

Figure 2.42

POEn# input pulse timing

POEn# input

(n = 0, 4, 8, 10, 11)

MTU PWM output pins

tPOEW

tPOEDI

Output disabled

Figure 2.43

Output disable time for POE in response to transition of the POEn# signal level

MTU PWM output pins

Simultaneous active-level outputs detected*1

Outputs

disabled

tPOEDO

Note 1. When the active level is set to low.

Figure 2.44

Output disable time for POE in response to the simultaneous conduction of output pins

RZ/N2L Datasheet

2. Electrical Characteristics

R01DS0397EJ0140 Rev.1.40

Mar 31, 2026

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