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RZ/N2L データシート(PDF) 93 Page - Renesas Technology Corp

部品番号 RZ/N2L
部品情報  RZ Arm-based High-end 32 & 64-bit MPUs
PDF  128 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RZ/N2L データシート(HTML) 93 Page - Renesas Technology Corp

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Table 2.37
ΔΣ interface timing
Parameter
Symbol
Min.
Max.
Unit
Reference figure
DSMIF
Clock cycle
Master
tDScyc
40
200
ns
Figure 2.78
Slave
40
200
Clock high level
Master
tDSCKWH
16
—
ns
Slave
16
—
Clock low level
Master
tDSCKWL
16
—
ns
Slave
16
—
Setup time
Master
tSU
15
—
ns
Figure 2.79, Figure 2.80
Slave
5
—
Hold time
Master
tH
0
—
ns
Slave
5
—
MCLKn
(n = 0 to 5)
tDScyc
tDSCKWH
tDSCKWL
Figure 2.78
Clock input/output timing
MCLKn
(input or output)
tSU
n = 0 to 5
MDATn
(input)
tH
Figure 2.79
Reception timing (MCLKn rising synchronous)
MCLKn
(input or output)
tSU
MDATn
(input)
tH
Figure 2.80
Reception timing (MCLKn falling synchronous)
2.5.5.14
Ethernet Interface Timing
Conditions:
VOH = VCC18 × 0.5, VOL = VCC18 × 0.5, C = 15 pF (RGMII)*1
RZ/N2L Datasheet
2. Electrical Characteristics
R01DS0397EJ0140 Rev.1.40
Mar 31, 2026
Page 93 of 128



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