OR4 datasheet(68/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

FPGA Conﬁguration Modes (continued)

Note: M3 = GND for high-speed CCLK; M3 = VDD for low-frequency CCLK.

5-9739(F).a

Figure 40. Asynchronous Peripheral Conﬁguration

Microprocessor Interface Mode

The built-in MPI in Series 4 FPGAs is designed for use in conﬁguring the FPGA. Figure 41 show the glueless inter-

face for FPGA conﬁguration and readback from the PowerPC processor. When enabled by the mode pins, the MPI

handles all conﬁguration/readback control and handshaking with the host processor. For single FPGA conﬁgura-

tion, the host sets the conﬁguration control register MPI_PRGM to one then back to zero and, after reading that the

conﬁguration write data acknowledge register is high, transfers data 8, 16, or 32 bits at a time to the FPGA’s D[#:0]

input pins. If conﬁguring multiple FPGAs through daisy-chain operation is desired, the SYS_DAISY bit must be set

in the conﬁguration control register of the MPI.

The conﬁguration control register offers control bits to enable the interrupt on a bit stream error. The MPI status

2-bit ﬁeld to indicate the bit stream error status. A ﬂow chart of the MPI conﬁguration process is shown in Figure 42.

MICRO-

PRGM

ORCA

SERIES

FPGA

DOUT

CCLK

HDC

LDC

VDD

TO DAISY-

CHAINED

DEVICES

PROCESSOR

D[7:0]

RDY/BUSY

INIT

DONE

ADDRESS

DECODE LOGIC

BUS

CONTROLLER

CS0

CS1

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