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OR4 データシート(PDF) 13 Page - Lattice Semiconductor |
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OR4 データシート(HTML) 13 Page - Lattice Semiconductor |
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13 / 152 page  Lattice Semiconductor 13 Data Sheet May, 2006 ORCA Series 4 FPGAs Programmable Logic Cells (continued) 5-9736(F)a Figure 7. MUX 8x1 Softwired LUT submode uses F4, F5 and F6 LUTs and internal PFU feedback routing to generate complex logic functions up to three LUT-levels deep. Multiplexers can be independently configured to route certain LUT outputs to the input of other LUTs. In this manner, very complex logic functions, some of up to 22 inputs, can be implemented in a single PFU at greatly enhanced speeds. It is important to note that an LUT output that is fed back for softwired use is still available to be registered or output from the PFU. This means, for instance, that a logic equation that is needed by itself and as a term in a larger equa- tion need only be generated once, and PLC routing resources will not be required to use it in the larger equation. K7_0 K7_1 K7_2 F5D LUT4 LUT4 K6_0 K6_1 K6_2 LUT4 LUT4 K5_0 K5_1 K5_2 K4_0 K4_1 K4_2 F5C LUT4 K3_0 K3_1 K3_2 F5B LUT4 LUT4 K2_0 K2_1 K2_2 LUT4 LUT4 K1_0 K1_1 K1_2 K0_0 K0_1 K0_2 F5A LUT4 MUX8x1 4x1 MUX 4x1 MUX [LUT647] MUX8x1 [LUT603] |
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