OR4 datasheet(2/152 Pages) LATTICE

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Table of Contents

Contents

Page

Contents

Page

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Introduction ................................................................ 1

Programmable Features ............................................ 1

System Features ....................................................... 4

Product Description ................................................... 5

Architecture Overview ..........................................5

Programmable Logic Cells ........................................ 6

Programmable Function Unit ...............................7

Look-Up Table Operating Modes .......................10

Supplemental Logic and Interconnect Cell ........20

PLC Latches/Flip-Flops ......................................24

Embedded Block RAM (EBR) .................................. 26

EBR Features ....................................................26

Routing Resources .................................................. 31

Clock Distribution Network ...................................... 31

Global Primary Clock Nets .................................31

Secondary Clock and Control Nets ....................31

Secondary Edge Clock Nets and

Fast Edge Clock Nets ...................................31

Cycle Stealing ....................................................32

Programmable Input/Output Cells (PIC) .................. 32

Programmable I/O ..............................................32

Inputs .................................................................35

Outputs ..............................................................36

I/O Banks and Groups ....................................... 37

Special Function Blocks .......................................... 39

Single Function Blocks .......................................47

Microprocessor Interface (MPI) ............................... 49

Embedded System Bus (ESB) ...........................49

Phase-Locked Loops (PLLs) ................................... 53

FPGA States of Operation ....................................... 56

Initialization ........................................................56

Power Supply Sequencing .................................57

Configuration ......................................................57

Start-Up ..............................................................57

Reconfiguration ..................................................61

Partial Reconfiguration .......................................61

Other Configuration Options ..............................61

Configuration Data Format .................................61

Using ispLEVER to Generate

Configuration RAM Data ...............................61

Configuration Data Frame ..................................62

Bit Stream Error Checking .................................64

FPGA Configuration Modes ..................................... 64

Master Parallel Mode .........................................65

Master Serial Mode ............................................66

Asynchronous Peripheral Mode .........................67

Microprocessor Interface Mode ..........................68

Slave Serial Mode ..............................................72

Slave Parallel Mode ...........................................72

Daisy-Chaining ...................................................73

Daisy-Chaining with Boundary-Scan ..................74

Absolute Maximum Ratings ..................................... 75

Recommended Operating Conditions ................75

Electrical Characteristics ......................................... 76

Power Estimation ..................................................... 77

Estimating Power Dissipation .................................. 77

Timing Characteristics ............................................. 78

Configuration Timing ..........................................92

Readback Timing ............................................ 100

Pin Information ...................................................... 101

Pin Descriptions .............................................. 101

Package Compatibility ..................................... 105

352-Pin PBGA Pinout ...................................... 107

416-Pin BGAM Pinout ..................................... 116

680-Pin PBGAM Pinout ................................... 126

Package Thermal Characteristics Summary ......... 142

ΘJA ................................................................. 142

ψJC ................................................................. 142

ΘJC ................................................................. 143

ΘJB ................................................................. 143

Package Thermal Characteristics .......................... 144

Package Coplanarity ............................................. 144

Heat Sink Vendors for BGA Packages .................. 144

Package Parasitics ................................................ 145

Package Outline Diagrams .................................... 146

Terms and Definitions ..................................... 146

352-Pin PBGA ................................................. 147

416-Pin PBGAM .............................................. 148

680-Pin PBGAM .............................................. 149

Ordering Information .............................................. 150

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