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OR4 データシート(PDF) 21 Page - Lattice Semiconductor |
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OR4 データシート(HTML) 21 Page - Lattice Semiconductor |
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21 / 152 page  Lattice Semiconductor 21 Data Sheet May, 2006 ORCA Series 4 FPGAs Programmable Logic Cells (continued) As discussed in the memory mode section, if the SLIC is placed into one of the modes where it contains both buffers and a decode or AOI function (e.g., BUF_BUF_DEC mode), the DEC output can be gated with the 3-state input signal. This allows up to a 6-input decode (e.g., BUF_DEC_DEC mode) plus the 3-state input to control the enable/disable of up to four buffers per SLIC Figure 15—Figure 19 show several configura- tions of the SLIC, while Table 5 shows all of the possi- ble modes. Table 5. SLIC Modes 5-5744(F).a. Figure 14. SLIC All Modes Diagram Mode No. Mode BUF [3:0] BUF [7:4] BUF [9:8] 1 BUFFER Buffer Buffer Buffer 2 BUF_BUF_DEC Buffer Buffer Decoder 3 BUF_DEC_BUF Buffer Decoder Buffer 4 BUF_DEC_DEC Buffer Decoder Decoder 5 DEC_BUF_BUF Decoder Buffer Buffer 6 DEC_BUF_DEC Decoder Buffer Decoder 7 DEC_DEC_BUF Decoder Decoder Buffer 8 DECODER Decoder Decoder Decoder SIN9 I9 SOUT09 DEC DEC 0/1 0/1 TRI 0/1 0/1 SOUT08 SOUT07 SOUT06 SOUT05 SOUT04 SOUT03 SOUT02 SOUT01 SOUT00 LOGIC 1 OR 0 SIN8 I8 LOGIC 1 OR 0 SIN7 I7 LOGIC 1 OR 0 SIN6 I6 LOGIC 1 OR 0 SIN5 I5 LOGIC 1 OR 0 SIN4 I4 LOGIC 1 OR 0 SIN3 I3 LOGIC 1 OR 0 SIN2 I2 LOGIC 1 OR 0 SIN1 I1 LOGIC 1 OR 0 SIN0 I0 LOGIC 1 OR 0 |
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