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HD151TS206SS データシート(PDF) 9 Page - Renesas Technology Corp

部品番号 HD151TS206SS
部品情報  Mother Board Clock Generator for Intel P4 Chipset (Springdale)
PDF  34 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD151TS206SS データシート(HTML) 9 Page - Renesas Technology Corp

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HD151TS206SS
Rev.1.00, Apr.28.2003, page 9 of 34
I
2C Controlled Register Bit Map (cont.)
Byte5 Control Register
Bit
Description
Contents
Type
Default
Note
7
48MHz Output Enable
0 = Disabled, 1 = Enabled
RW
1
6
Reserved
RW
1
5
VCH Select 66MHz / 48MHz
0 = 3V66 mode
1 = VCH (48MHz) mode
RW
0
4
Reserved
RW
1
3
3V66_3/VCH Output Enable
0 = Disabled, 1 = Enabled
RW
1
2
3V66_2 Output Enable
0 = Disabled, 1 = Enabled
RW
1
1
3V66_1 Output Enable
0 = Disabled, 1 = Enabled
RW
1
0
3V66_0 Output Enable
0 = Disabled, 1 = Enabled
RW
1
Byte6 Control Register
Bit
Description
Contents
Type
Default
Note
7
Test Clock Mode
0 = Disabled, 1 = Enabled
RW
0
6
Reserved
RW
0
5
Reserved
RW
0
4
SRC Frequency Select
0 = 100 MHz, 1 = 200 MHz
RW
0
3
Reserved
RW
0
2
Spread Spectrum Mode
0 = Spread OFF
1 = Spread ON
RW
0
See
B9[7:6]
1
REF1 Output Enable
0 = Disabled, 1 = Enabled
RW
1
0
REF0 Output Enable
0 = Disabled, 1 = Enabled
RW
1
Byte7 Vendor Identification Register
Bit
Description
Contents
Type
Default
Note
7
Revision Code Bit3
Vendor Specific
R
0
6
Revision Code Bit2
Vendor Specific
R
0
5
Revision Code Bit1
Vendor Specific
R
0
4
Revision Code Bit0
Vendor Specific
R
1
3
Vendor ID Bit3
Vendor Specific
R
1
2
Vendor ID Bit2
Vendor Specific
R
1
1
Vendor ID Bit1
Vendor Specific
R
1
0
Vendor ID Bit0
Vendor Specific
R
1



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