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HD404339FS データシート(PDF) 14 Page - Renesas Technology Corp

部品番号 HD404339FS
部品情報  microcomputer with large-capacity memory designed to
PDF  80 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD404339FS データシート(HTML) 14 Page - Renesas Technology Corp

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HD404339 Series
12
IE
IM
LSON
IAOF
IF
ICSF
ICEF
RAME
RSP
WDON
ADSF
DTON
Not used
SEM/SEMD
Not executed
Allowed
Allowed
REM/REMD
TM/TMD
Allowed
Allowed
Allowed
Not executed
Allowed
Allowed
Not executed in active mode
Used in subactive mode
Not executed
Allowed
Not executed
Inhibited
Allowed
Not executed
Inhibited
Inhibited
Allowed
Allowed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instruction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode. If the TM or TMD instruction is executed for
the inhibited bits or non-existing bits, the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
Memory registers
$040
$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F
$3C0
$3FF
MR(0)
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
ST
PC
CA
PC
10
3
13
9
6
2
12
8
5
1
11
7
4
0
Bit 3
Bit 2
Bit 1
Bit 0
PC –PC :
ST: Status flag
CA: Carry flag
Program counter
13
Stack area
0
$3FC
$3FD
$3FE
$3FF
Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position



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