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HD64F2149YV データシート(PDF) 566 Page - Renesas Technology Corp

部品番号 HD64F2149YV
部品情報  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV データシート(HTML) 566 Page - Renesas Technology Corp

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Section 16 I
2C Bus Interface
Rev. 3.00 Jan 18, 2006 page 538 of 1044
REJ09B0280-0300
16.3.9
Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 16.12 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
System clock
period
Sampling clock
C
DQ
Latch
C
DQ
Latch
SCL or
SDA input
signal
Match
detector
Internal
SCL or
SDA
signal
Sampling
clock
Figure 16.13 Block Diagram of Noise Canceler
16.3.10
Sample Flowcharts
Figures 16.13 to 16.16 show sample flowcharts for using the I
2C bus interface in each mode.



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