HD64F2149YV datasheet(567/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 539 of 1044

REJ09B0280-0300

Start

End

Initialize

Read BBSY in ICCR

Read IRIC in ICCR

Read ACKB in ICSR

Write transmit data in ICDR

Clear IRIC in ICCR

Read ACKB in ICSR

Clear IRIC in ICCR

Read IRIC in ICCR

Write transmit data in ICDR

Master receive mode

Set MST = 1 and

TRS = 1 in ICCR

Write BBSY = 0

and SCP = 0 in ICCR

Write BBSY = 1 and

SCP = 0 in ICCR

BBSY = 0 ?

IRIC = 1 ?

ACKB = 0 ?

Yes

IRIC = 1 ?

Yes

Transmit mode ?

IRIC = 1 ?

End of transmission ?

or ACKB = 1 ?

Yes

[2]

Test the status of the SCL and SDA lines.

[3]

Select master transmit mode.

[4]

Start condition issuance

[6]

Set transmit data for the first byte

(slave address + R/

W).

(After writing ICDR, clear IRIC

immediately)

[1]

Initialize

[8]

Test the acknowledge bit,

transferred from slave device.

[5]

Wait for a start condition

[7]

Wait for 1 byte to be transmitted.

[10] Wait for 1 byte to be transmitted.

[11] Test for end of transfer

[12] Stop condition issuance

[9]

Set transmit data for the second and

subsequent bytes.

(After writing ICDR, clear IRIC immediately.)

Figure 16.14 Flowchart for Master Transmit Mode (Example)

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