H8SXSLASH1663 datasheet(911/1158 Pages) RENESAS

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Section 18 A/D Converter

Rev.1.00 Jun. 07, 2006 Page 859 of 1102

REJ09B0294-0100

18.4.3

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input when the A/D conversion start delay time (t

D) passes after the ADST bit in ADCSR is set to

1, then starts A/D conversion. Figure 18.4 shows the A/D conversion timing. Table 18.3 indicates

the A/D conversion time.

As indicated in figure 18.4, the A/D conversion time (t

CONV) includes tD and the input sampling time

SPL). The length of tD varies depending on the timing of the write access to ADCSR. The total

conversion time therefore varies within the ranges indicated in table 18.3.

In scan mode, the values given in table 18.3 apply to the first conversion time. The values given in

table 18.4 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in

ADCR should be set so that the conversion time is within the ranges indicated by the A/D

conversion characteristics.

(1)

(2)

tSPL

tCONV

Address

Write signal

Input sampling

timing

ADF

[Legend]

(1):

ADCSR write cycle

(2):

ADCSR address

tD:

A/D conversion start delay time

tSPL:

Input sampling time

tCONV: A/D conversion time

Figure 18.4 A/D Conversion Timing

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