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H8SX/1663 データシート(PDF) 147 Page - Renesas Technology Corp |
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H8SX/1663 データシート(HTML) 147 Page - Renesas Technology Corp |
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147 / 1158 page  Section 5 Interrupt Controller Rev.1.00 Jun. 07, 2006 Page 95 of 1102 REJ09B0294-0100 5.2 Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable External Interrupt Rising or falling edge can be selected. IRQ11 to IRQ0 Input Maskable External Interrupts Rising, falling, or both edges, or level sensing, can be independently selected. 5.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) • CPU priority control register (CPUPCR) • Interrupt priority registers A to C, E to I, K, L, Q, and R (IPRA to IPRC, IPRE to IPRI, IPRK, IPRL, IPRQ, and IPRR) • IRQ enable register (IER) • IRQ sense control registers H and L (ISCRH, ISCRL) • IRQ status register (ISR) • Software standby release IRQ enable register (SSIER) |
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