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H8SX/1663 データシート(PDF) 248 Page - Renesas Technology Corp

部品番号 H8SX/1663
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663 データシート(HTML) 248 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 196 of 1102
REJ09B0294-0100
(2) 16-Bit 3-State Access Space
Figures 6.18 to 6.20 show the bus timing of 16-bit 3-state access space.
When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even
addresses, and the lower byte data bus (D7 to D0) is used for odd addresses. Wait cycles can be
inserted.
Valid
Invalid
T
1
T
2
T
3
Address
CSn
AS
RD
DACK
D15 to D8
D7 to D0
D15 to D8
D7 to D0
LHWR
LLWR
High level
High-Z
B
φ
Bus cycle
Valid
BS
RD/
WR
Read
Write
1. n = 0 to 7
2. When RDNn = 0
3. When DKC = 0
Notes:
Figure 6.18 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address)



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