SH7052 datasheet(408/919 Pages) RENESAS

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Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7): An example of the

setup procedure for PWM timer operation (channels 6 and 7) is shown in figure 10.60.

1. Set the first-stage counter clock ø' in prescaler register 2 and 3 (PSCR2, PSCR3), and select the

second-stage counter clock ø" with the CKSEL bit in the timer control register (TCR6A,

TCR6B, TCR7A, TCR7B).

2. Set the port B control register L (PBCRL) corresponding to the waveform output port to ATU

PWM output. Also set the corresponding bit to 1 in the port B IO register (PBIOR) to specify

the output attribute.

3. Set PWM waveform output 1 output timing in the cycle register (CYLR6A to CYLR6D,

CYLR7A to CYLR7D), and set the PWM waveform output 0 output timing in the buffer

DTR7A to DTR7D). If necessary, an interrupt request can be sent to the CPU on a compare-

match between the CYLR value and the free-running counter (TCNT) value by making the

appropriate setting in the timer interrupt enable register (TIER). In addition, setting the DMAC

allows DMAC activation to be performed.

4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the TCNT counter for

the relevant channel.

Notes: 1. Do not make a setting in DTR after the counter is started. Use BFR to make a DTR

setting.

2. 0% duty is specified by setting H'0000 in the duty register (DTR), and 100% duty is

specified by setting buffer register (BFR) = cycle register (CYLR). Do not set BFR >

CYLR.

SH7052 データシート(PDF) 408 Page - Renesas Technology Corp