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AD9522-2 データシート(PDF) 13 Page - Analog Devices |
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AD9522-2 データシート(HTML) 13 Page - Analog Devices |
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13 / 84 page  AD9522-2 Rev. 0 | Page 13 of 84 SERIAL CONTROL PORT—I²C MODE Table 14. Parameter Min Typ Max Unit Test Conditions/Comments SDA, SCL (WHEN INPUTTING DATA) Input Logic 1 Voltage 0.7 × VS V Input Logic 0 Voltage 0.3 × VS V Input Current with an Input Voltage Between 0.1 × VS and 0.9 × VS −10 +10 μA Hysteresis of Schmitt Trigger Inputs 0.015 × VS V Pulse Width of Spikes That Must Be Suppressed by the Input Filter, tSPIKE 50 ns SDA (WHEN OUTPUTTING DATA) Output Logic 0 Voltage at 3 mA Sink Current 0.4 V Output Fall Time from VIHMIN to VILMAX with a Bus Capacitance from 10 pF to 400 pF 20 + 0.1 Cb 250 ns Cb = capacitance of one bus line in pF TIMING Note that all I2C timing values refer to VIHMIN (0.3 × VS) and VILMAX levels (0.7 × VS) Clock Rate (SCL, fI2C) 400 kHz Bus Free Time Between a Stop and Start Condition, tIDLE 1.3 μs Setup Time for a Repeated Start Condition, tSET; STR 0.6 μs Hold Time (Repeated) Start Condition (After This Period, the First Clock Pulse Is Generated), tHLD; STR 0.6 μs Setup Time for Stop Condition, tSET; STP 0.6 μs Low Period of the SCL Clock, tLOW 1.3 μs High Period of the SCL Clock, tHIGH 0.6 μs SCL, SDA Rise Time, tRISE 20 + 0.1 Cb 300 ns Cb = capacitance of one bus line in pF SCL, SDA Fall Time, tFALL 20 + 0.1 Cb 300 ns Cb = capacitance of one bus line in pF Data Setup Time, tSET; DAT 120 ns This is a minor deviation from the original I²C specification of 100 ns minimum Data Hold Time, tHLD; DAT 140 880 ns This is a minor deviation from the original I²C specification of 0 ns minimum1 Capacitive Load for Each Bus Line, Cb 400 pF 1 According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL falling edge. |
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