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AD9522-2 データシート(PDF) 18 Page - Analog Devices |
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AD9522-2 データシート(HTML) 18 Page - Analog Devices |
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18 / 84 page  AD9522-2 Rev. 0 | Page 18 of 84 Pin No. Input/ Output Pin Type Mnemonic Description 15 I 3.3 V CMOS CS Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor. 16 I 3.3 V CMOS SCLK/SCL Serial Control Port Clock Signal. This pin has an internal 30 kΩ pull-down resistor in SPI mode but is high impedance in I²C mode. 17 I/O 3.3 V CMOS SDIO/SDA Serial Control Port Bidirectional Serial Data In/Out. 18 O 3.3 V CMOS SDO Serial Control Port Unidirectional Serial Data Out. 19, 59 I GND GND Ground Pins. 20 I Three-level logic SP1 Select SPI or I²C as the serial interface port and select the I²C slave address in I²C mode. Three-level logic. This pin is internally biased for the open logic level. 21 I Three-level logic SP0 Select SPI or I²C as the serial interface port and select the I²C slave address in I²C mode. Three-level logic. This pin is internally biased for the open logic level. 22 I 3.3 V CMOS EEPROM Setting this pin high selects the register values stored in the internal EEPROM to be loaded at reset and/or power-up. Setting this pin low causes the AD9522 to load the hard-coded default register values at power-up/reset. This pin has an internal 30 kΩ pull-down resistor. 23 I 3.3 V CMOS RESET Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor. 24 I 3.3 V CMOS PD Chip Power-Down, Active Low. This pin has an internal 30 kΩ pull-up resistor. 25 O LVDS or CMOS OUT9 (OUT9A) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 26 O LVDS or CMOS OUT9 (OUT9B) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 28 O LVDS or CMOS OUT10 (OUT10A) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 29 O LVDS or CMOS OUT10 (OUT10B) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 30 O LVDS or CMOS OUT11 (OUT11A) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 31 O LVDS or CMOS OUT11 (OUT11B) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 33 O LVDS or CMOS OUT6 (OUT6A) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 34 O LVDS or CMOS OUT6 (OUT6B) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 36 O LVDS or CMOS OUT7 (OUT7A) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 37 O LVDS or CMOS OUT7 (OUT7B) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 38 O LVDS or CMOS OUT8 (OUT8A) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 39 O LVDS or CMOS OUT8 (OUT8B) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 42 O LVDS or CMOS OUT5 (OUT5B) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 43 O LVDS or CMOS OUT5 (OUT5A) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 44 O LVDS or CMOS OUT4 (OUT4B) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. 45 O LVDS or CMOS OUT4 (OUT4A) Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. |
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