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AD9522-2 データシート(PDF) 28 Page - Analog Devices

部品番号 AD9522-2
部品情報  12 LVDS/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO
PDF  84 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9522-2 データシート(HTML) 28 Page - Analog Devices

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AD9522-2
Rev. 0 | Page 28 of 84
PROGRAMMABLE
N DELAY
REFIN
CLK
CLK
REF1
REF2
BUF
AMP
AD9522
STATUS
REFERENCE
SWITCHOVER
REF_SEL
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
HOLD
0
1
DIVIDE BY 1,
2, 3, 4, 5, OR 6
PD
SYNC
REFIN
RESET
EEPROM
DIGITAL
LOGIC
EEPROM
DIVIDE BY
1 TO 32
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
DIVIDE BY
1 TO 32
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
DIVIDE BY
1 TO 32
OUT6
OUT6
OUT7
OUT7
OUT8
OUT8
DIVIDE BY
1 TO 32
OUT9
OUT9
OUT10
OUT10
OUT11
OUT11
ZERO DELAY BLOCK
STATUS
STATUS
SP1
SP0
SPI
INTERFACE
I2C
INTERFACE
SCLK/SCL
SDIO/SDA
SDO
CS
SERIAL
PORT
DECODE
OPTIONAL
Figure 37. Internal VCO and Clock Distribution (Mode 0)



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