LTC2926IGN datasheet(14/28 Pages) LINER

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LTC2926

2926fa

Status Output

The output aspect of the STATUS/PGI pin allows the

LTC2926 to control and communicate with external

downstream circuits. The pin is driven internally by an

N-channel MOSFET pull-down to GND and a 10µA pull-

up to an internal charge pump. The pull-down keeps the

STATUS/PGI pin low until MGATE, SGATE1 and SGATE2

are fully enhanced, and the remote sense switches are

closed. The pull-down then shuts off, and STATUS/PGI

pin rises, indicating to downstream monitors that the

supplies are fully ramped up. The STATUS/PGI pin pulls

low when the MGATE, SGATE1, SGATE2 or RSGATE pin

is low, either because a fault has been latched, or because

the ON pin is low.

An internal charge pump rail at VCC + 5.5V sources the

STATUS/PGI pull-up current. An external resistor may be

added to create logic level voltages, or the pin may be

used to enhance the gates of external N-channel MOSFET

switches, if desired.

Power Good Timeout

The input aspect of the STATUS/PGI pin allows external

downstream monitoring circuits to control the LTC2926 as

shown in Figure 9. The power good timeout circuit discon-

nects the supply generators if for any reason the voltage

level of the STATUS/PGI pin is not high after the timeout

period. During a ramp-up, the timeout circuit will trip if the

internal pull-down on STATUS/PGI fails to release, which

indicates that supply ramping was not completed in the

time allotted. If supply ramping completes, any downstream

circuits that pull down the STATUS/PGI pin after the timer

duration also will trip the timeout circuit. A fault caused

by a power good timeout has the same effect as a fault

triggered by the FAULT pin: supplies are disconnected

and the fault latch is set. The fault latch may be cleared as

described in the Fault Input/Output section above.

The power good timer duration is conﬁgured by a capacitor

tied between PGTMR and GND. The pin’s 10µA current

source ramps up the capacitor voltage when the ON pin is

high, otherwise 4mA pulls PGTMR to GND. The capacitor,

CPGTMR, required to conﬁgure the power good timeout

duration, tPGTMR, is determined from:

PGTMR

123

•

If the power good timeout feature is not used, tie PGTMR

to GND.

Retry on Fault

The LTC2926 continuously attempts to ramp up the supplies

after a fault if the FAULT pin is tied to the ON pin. When

the FAULT and ON pins go low together, the internal fault

latch is set by the falling FAULT pin, and the fault latch is

reset by the falling ON pin. A short internal delay of several

microseconds guarantees triggering of fast pull-down

circuits on the RSGATE, MGATE, SGATE1 and SGATE2

pins, which opens the remote sense switches and discon-

nects the master and slave supplies before the fault latch

is reset. If no external signal pulls down the FAULT pin,

the internal 8.5µA pull-up current or an external pull-up

resistor increases the ON (and FAULT) pin voltage above

0.6V, which arms the fault latch. A ramp-up begins when

ON is above 1.23V.

In applications where the LTC2926 is conﬁgured for fault

retry, some details of the retry behavior are determined by

the source and duration of the fault signal. When a fault

is triggered by an external pull-down signal on the FAULT

(and ON) pin, supply ramping will not restart until the low

input ceases. When a power good fault is triggered by an

external pull-down signal on the STATUS/PGI pin, supply

ramping restarts immediately. If the low signal persists

APPLICATIO S I FOR ATIO

Figure 9. External Load Monitor Controlling LTC2926 via Power

Good Input

2926 F09

LTC2926

FB1

GND PGTMR

CPGTMR

STATUS/PGI

ON/OFF

SGATE2

Ω

SGATE1

Ω

RFB1

RFA1

FB2

RFB2

RFA2

RST

TOL

RST

GND

1.8V

SOURCE

1.8V

SLAVE1

2.5V

SOURCE

2.5V

SLAVE2

LTC2904

LOAD VOLTAGE

MONITOR

(10% TOLERANCE)

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