MFRC522 datasheet(40/96 Pages) NXP

40 / 96 page

MFRC522_33

Product data sheet

PUBLIC

Rev. 3 — 26 October 2009

112133

40 of 96

NXP Semiconductors

MFRC522

Contactless reader IC

9.3.1.8

Status1Reg register

Contains status bits of the CRC, interrupt and FIFO buffer.

Table 35.

Status1Reg register (address 07h); reset value: 21h bit allocation

Bit

Symbol

reserved

CRCOk CRCReady

IRq

TRunning

reserved

HiAlert

LoAlert

Access

Table 36.

Status1Reg register bit descriptions

Bit Symbol

Value Description

reserved

reserved for future use

CRCOk

the CRC result is zero

for data transmission and reception, the CRCOk bit is undeﬁned: use the

ErrorReg register’s CRCErr bit

indicates the status of the CRC coprocessor, during calculation the

value changes to logic 0, when the calculation is done correctly the

value changes to logic 1

CRCReady 1

the CRC calculation has ﬁnished

only valid for the CRC coprocessor calculation using the CalcCRC

command

IRq

indicates if any interrupt source requests attention with respect to the

setting of the interrupt enable bits: see the ComIEnReg and DivIEnReg

registers

TRunning

MFRC522’s timer unit is running, i.e. the timer will decrement the

TCounterValReg register with the next timer clock

Remark: in gated mode, the TRunning bit is set to logic 1 when the

timer is enabled by TModeReg register’s TGated[1:0] bits; this bit is not

inﬂuenced by the gated signal

reserved

reserved for future use

HiAlert

the number of bytes stored in the FIFO buffer corresponds to equation:

example:

FIFO length = 60, WaterLevel = 4

→ HiAlert = 1

FIFO length = 59, WaterLevel = 4

→ HiAlert = 0

LoAlert

the number of bytes stored in the FIFO buffer corresponds to equation:

example:

FIFO length = 4, WaterLevel = 4

→ LoAlert = 1

FIFO length = 5, WaterLevel = 4

→ LoAlert = 0

HiAlert

FIFOLength

–

)

(

WaterLevel

≤

LoAlert

FIFOLength

WaterLevel

≤

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