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AT697F データシート(PDF) 48 Page - ATMEL Corporation |
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AT697F データシート(HTML) 48 Page - ATMEL Corporation |
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48 / 155 page  48 7703C–AERO–6/09 AT697F ADVANCE INFORMATION Watchdog The watchdog operates the same way as the timers, with the difference that it is always enabled and upon underflow asserts the external signal WDOG. This signal can be used to generate a system reset. If the watchdog counter is refreshed by writing to WDG register before the counter reaches zero, the coun- ter restarts counting from the new value. If the counter is not refreshed before the counter reaches zero, WDOG signal is asserted. After reset, the watchdog is automatically enabled and starts running. The watchdog is reset to a “all ones”. Together with the default prescaler ratio of 4, the time until first expiration of the watchdog after reset is about 2^34 clock cycles. Note: A read access gives the decounting value of the watchdog, the reload value itself is not stored in the processor. Figure 32. Watchdog Block Diagram Control Logic Watchdog Reg. =0xFFFFFFFF clock WDG WDOG |
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