ATmega16HVB datasheet(22/273 Pages) ATMEL

22 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other-

wise no EEPROM write takes place. The following procedure should be followed when writing

the EEPROM (the order of steps 2 and 3 is not essential):

Wait until EEPE becomes zero.

Write new EEPROM address to EEAR (optional).

Write new EEPROM data to EEDR (optional).

Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

Within four clock cycles after setting EEMPE, write a logical one to EEPE.

Caution:

An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master

Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another

EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted

EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all

the steps to avoid these problems.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft-

ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set,

the CPU is halted for two cycles before the next instruction is executed.

Caution:

A BOD reset during EEPROM write will invalidate the result of the ongoing operation.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct

address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in

progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses and the programming time will

therefore depend on the calibrated oscillator frequency. Table 8-2 lists the typical programming

time for EEPROM access from the CPU.

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob-

ally) so that no interrupts will occur during execution of these functions. The examples also

assume that no Flash Boot Loader is present in the software. If such code is present, the

EEPROM write function must also wait for any ongoing SPM command to finish.

Table 8-2.

EEPROM Programming Time

Symbol

Number of Calibrated RC

Oscillator Cycles

Typ Programming Time,

fOSC = 8 MHz

EEPROM write

(from CPU)

27200

3.4 ms

ATmega16HVB データシート(PDF) 22 Page - ATMEL Corporation

ATmega16HVB データシート(HTML) 22 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード