ATmega16HVB datasheet(28/273 Pages) ATMEL

28 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

To determine the accurate clock period as a function of die temperature, if needed by the

application, the Oscillator Sampling Interface should be used. Refer to section ”OSI –

Oscillator Sampling Interface” on page 29 for details.

To determine a fixed value for the actual clock period independent of the die temperature,

for example to determine the best setting of the Battery Protection timing, use the calibra-

tion byte ULP_RC_FRQ stored in the signature address space, refer to section ”Reading

the Signature Row from Software” on page 199 for details.

9.3

Clock Startup Sequence

When the CPU wakes up from Power-save, the CPU clock source is used to time the start-up,

ensuring a stable clock before instruction execution starts. When the CPU starts from reset,

there is an additional delay allowing the voltage regulator to reach a stable level before com-

mencing normal operation. The Ultra Low Power RC Oscillator is used for timing this real-time

part of the start-up time. Start-up times are determined by the SUT Fuses as shown in Table 9-2

on page 27. The number of Ultra Low Power RC Oscillator cycles used for each time-out is

shown in Table 9-3.

Note:

1. The actual value depends on the actual clock period of the Ultra Low Power RC Oscillator,

refer to ”Ultra Low Power RC Oscillator” on page 27 for details.

9.4

Clock Output

The CPU clock divided by 2 can be output to the PB1 pin. The CPU can enable the clock output

function by setting the CKOE bit in the MCU Control Register. The clock will not run in any sleep

modes.

9.5

System Clock Prescaler

The ATmega16HVB/32HVB has a System Clock Prescaler, used to prescale the Calibrated Fast

RC Oscillator. The system clock can be divided by setting the ”CLKPR – Clock Prescale Regis-

ter” on page 32, and this enables the user to decrease or increase the system clock frequency

as the requirement for power consumption and processing power changes. This system clock

will affect the clock frequency of the CPU and all synchronous peripherals. clk

I/O, clkCPU and clk-

FLASH are divided by a factor as shown in Table 9-4 on page 33.

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than

Table 9-3.

Number of Ultra Low Power RC Oscillator Cycles

Typ Time-out(1)

Number of Cycles

4 ms

512

8 ms

16 ms

32 ms

64 ms

128 ms

16K

256 ms

32K

512 ms

64K

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